Open the Processors!

My bachelor’s degree was focused on computer architecture and logical design, and even though I don’t work in that field now, I still have a love for it.

When I had a chance, I would sometimes implement “soft” processors within programmable logic and get them to operate in the context of a whole lot of custom programmable logic. This included programming them in assembly language or even trying to create a “C” compiler for it (a bit of a hopeless cause, as it turns out).

Companies such as Intel of course justifiably have a closed architecture that they own, and they only release what information is needed by their customers. Of course, they fabricate and sell the physical processors.

In contrast, companies such as ARM Ltd also have a closed design and closed architecture, but do not produce any physical processors. Instead they license the design to manufacturers who sell the physical products.

A few years ago i first heard about RISC-V which was just coming out but there were no physical processors at the time. What was really noteworthy was that this was to be an open source processor architecture, which would greatly expand the ways in which CPU geeks like myself could interact with it, experiment with it, and use it for practical projects as well as commercial products. I remember hoping at the time that they would come out with a “soft” processor in VHDL or Verilog so that I could play with it. I was in the midst of my own processor design at the time (totally a side project) and thought I could learn a lot from the RISC-V.

After hearing no more about the architecture for years, I was floored when I realized that some of the new microcontrollers coming out were RISC-V architecture, and that this was the same open architecture that I had run into before. I spent a little more time learning about the details, and I was glad to see that its design more or less aligned with my own particular set of ideal principles. The instruction set is relatively sparse and uncomplicated, as befits a Reduced Instruction Set Computing (RISC) architecture.

The instruction set design is very efficient, orthogonal (meaning that there is little duplication of similar function to different instructions), and modular, which means that it is easily separated into different categories of instructions. Taking this modularity to another level, these categories of instructions are not implemented in every version of the processor. For example, floating point division is implemented in an “G” capability processor, but not an “I” capability processor. The instruction subgroups making up each chunk of capability are frozen early in the design process, making sure that an instruction that works in this year’s processor doesn’t break in next year’s processor. Finally, every instruction is decoded, and those not implemented in the current design generate an interrupt, which can be used to handle the unimplemented functions in software.

I am really glad to see some of these open source hardware projects make it big. Clearly the world has greatly benefited from open source software. Much of today’s software would not be possible without the ability to build upon the work of others, which would be economically impossible in a world of fully proprietary software. Having open source processors helps ensure processors free of bugs due to greater scrutiny of the low level implementation, helping avoid problems like the Heartbleed bug. It also allows makers without huge bank accounts to fill in and customize more of the system solution on their own, allowing for more exploration and discoveries which often lead to great things. So my hat is off to you, RISC-V designers at UCB, for making this possible.